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ispGDS22/18/14
in-system programmable Generic Digital Switch
TM
Features
* HIGH-SPEED SWITCH MATRIX -- 7.5 ns Maximum Propagation Delay -- Typical Icc = 25 mA -- UltraMOS(R) Advanced CMOS Technology * FLEXIBLE I/O MACROCELL -- Any I/O Pin Can be Input, Output, or Fixed TTL High or Low -- Programmable Output Polarity -- Multiple Outputs Can be Driven by One Input * IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY) -- Programming Time of Less Than One Second -- 4-Wire Programming Interface -- Minimum 10,000 Program/Erase Cycles * E2 CELL TECHNOLOGY -- Non-Volatile Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * APPLICATIONS INCLUDE: -- Software-Driven Hardware Configuration -- Multiple DIP Switch Replacement -- Software Configuration of Add-In Boards -- Configurable Addressing of I/O Boards -- Multiple Clock Source Selection -- Cross-Matrix Switch * ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram (ispGDS22)
A0 A1 A2 A3 I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell
Bank A
A4 A5 A6 A7 A8 A9 A10
PROGRAMMABLE SWITCH MATRIX
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell B1
B10
B9
B8
B7
B6
B5
B4
B3
B2
Bank B I/O Cell
Closed only when C0=1 and C1=0 Vcc 4:1 MUX 01 Switch Matrix 10 11 00 C2 C1 C0
Description
The Lattice Semiconductor ispGDSTM family is an ideal solution for reconfiguring system signal routing or replacing DIP switches used for feature selection. With today's demands for customer ease of use, there is a need for hardware which is easily reconfigured electronically without dismantling the system. The ispGDS devices address this challenge by replacing conventional switches with a software configurable solution. Since each I/O pin can be set to an independent logic level, the ispGDS devices can replace most DIP switch functions with about half the pin count, and without the need for additional pull-up resistors. In addition to DIP switch replacement, the ispGDS devices are useful as signal routing cross-matrix switches. This is the only non-volatile device on the market which can provide this flexibility. With a maximum tpd of 7.5ns, and a typical active Icc of only 25 mA, these devices provide maximum performance at very low power levels. The ispGDS devices may be programmed in-system, using 5 volt only signals, through a simple 4-wire programming interface. The ispGDS devices are manufactured using Lattice Semiconductor's advanced non-volatile E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. Each I/O macrocell can be configured as an input, an inverting or non-inverting output, or a fixed TTL high or low output. Any I/O pin can be driven by any other I/O pin in the opposite bank. A single input can drive one or more outputs in the opposite bank, allowing a signal (such as a clock) to be distributed to multiple destinations on the board, under software control. The I/Os accept and drive TTL voltage levels. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor is able to deliver 100% field programmability and functionality of all Lattice Semiconductor products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified.
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com
July 1997
ispgds_02
B0
I/O Cell
Specifications ispGDS
ispGDS Ordering Information
Commercial Grade Specifications
Matrix Size 11 x 11 9x9 7x7 I/O Pins 22 18 14 Tpd (ns) 7.5 7.5 7.5 Isb (mA) 25 25 25 Icc (mA) 40 40 40 Ordering # ispGDS22-7P ispGDS22-7J ispGDS18-7P ISPGDS14-7P ispGDS14-7J Package 28-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 20-Pin Plastic DIP 20-Lead PLCC
Part Number Description
XXXXXXXX _ XX XX
ispGDS22 Device Name ispGDS18 ispGDS14 Speed (ns)
Grade
Blank = Commercial
Package P = Plastic DIP J = PLCC
2
Specifications ispGDS
Pin Configuration
28-Pin DIP
A0 A1 A2 SDI A3 A4 Vcc A5 A6 A7 MODE A8 A9 A10 14 15 1 28 B0 B1 B2 SDO B3
24-Pin DIP
A0 A1 A2 SDI A3 Vcc A4 A5 MODE A6 A7 A8 12 13 6 18 1 24 B0 B1 B2 SDO
20-Pin DIP
A0 A1 A2 SDI Vcc A3 MODE A4 A5 A6 10 11 1 20 B0 B1 B2 SDO
ispGDS 22
7 21
ispGDS 18
B3 B4 GND B5 SCLK B6 B7 B8
ispGDS 5 14
15
B3 GND SCLK B4 B5 B6
B4 B5 GND B6 B7 SCLK B8 B9 B10
28-Pin PLCC
SDI A2 A1 A0 B0 B1 B2
20-Pin PLCC
A2 A1 2 A0 B0 20 18 B2 SDO 6 B1
4 A3 A4 Vcc A5 A6 A7 MODE 11 12
A8 A9
2
28
26 25 SDO B3
SDI Vcc A3 MODE A4 8 4
5
7
ispGDS22
9
23
B4 B5
ispGDS14
16
B3 GND
21
GND B6
10 A5 A6 B6 12 B5 B4
14
SCLK
14
A10 B10
16
B9 B8
19 18
SCLK
B7
3
Specifications ispGDS
ispGDS Family Overview
There are three members of the ispGDS family, the ispGDS22, ispGDS18, and ispGSD14. The numerical portion of the part name indicates the number of I/O cells available. All of the devices are available in a DIP package, with the ispGDS22 and ispGDS14 also available in a PLCC package. Each of the devices operate identically, with the only difference being the number of I/O cells available. The ispGDS devices are all programmed through a four-pin interface, using TTL level signals. The four dedicated programming pins are named MODE, SDI, SDO, and SCLK. No highvoltage is needed, as the voltages needed for programming are generated internally. Programming of the entire device, including erasure, can be done in less than one second. During the programming operation, all I/O pins will be tri-stated. Further details of the programming process can be found in the InSystem Programming section later in this datasheet. The I/O cells in each device are divided equally into two banks (Bank A and Bank B). Each I/O cell can be configured as an input, an inverting output, a non-inverting output, or set to a fixed TTL high or low. A switch matrix connects the I/O banks, allowing an I/O cell in one bank to be connected to any of the I/ O cells in the other bank. A single I/O cell configured as an input can drive one or more I/O cells in the other bank. The full I/O macrocell, which is identical for each of the I/O pins, is shown below. The allowable configurations are shown on the following page.
Device Programming
The ispGDS family of devices uses a standard JEDEC file, as used for programmable logic devices, to describe device programming information. Popular logic compilers, such as ABEL and CUPL, can produce the JEDEC files for these devices. The JEDEC files can be used to program the ispGDS devices in a number of ways, which are shown in the section titled ISP Architecture and Programming.
Electronic Signature
An electronic signature word is provided with every ispGDS device. It contains 32 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the fuse checksum in the JEDEC fusemap.
In-System Programmability
The ispGDS family of devices feature In-System Programmable technology. By integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. All necessary programming is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. The interface signals are Serial Data In (SDI), Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control. For details on the operation of the internal state machine and programming of ispGDS devices please refer to the ISP Architecture and Programming section in this Data Book.
4
Specifications ispGDS
I/O Macrocell
Closed only when C0=1 and C1=0 Vcc 4:1 MUX 01 Switch Matrix 10 11 00 C2 C1 C0
I/O Macrocell Configurations
Configuration for Active High Output
From Switch Matrix
- C0 = 0. - C1 = 1. - C2 = 1.
Configuration for Active Low Output
From Switch Matrix
- C0 = 0. - C1 = 0. - C2 = 1.
Configuration for Fixed TTL High Output
Vcc
- C0 = 0. - C1 = 1. - C2 = 0.
Configuration for Fixed TTL Low Output - C0 = 0. - C1 = 0. - C2 = 0.
Configuration for Dedicated Input
To Switch Matrix
- C0 = 1. - C1 = 0. - C2 = 1.
Note 1: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Note 2: The default configuration for unused pins is for all configuration bits set to one, which produces a tri-stated output.
5
Specifications ispGDS
Absolute Maximum Ratings(1)
Supply voltage VCC ........................................ -.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Cond.
Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.2 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -10 10 0.5 -- 8 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL IIH VOL VOH IOL IOH IOS1
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ISB Standby Power
Supply Current
Inputs = 0V
Outputs open
L-7
--
15
25
mA
ICC
Operating Power Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -7
--
25
40
mA
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 5V and TA = 25 C
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI/O PARAMETER I/O Capacitance (as input or output) MAXIMUM* 8 UNITS pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V
*Characterized but not 100% tested.
6
Specifications ispGDS
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER
TEST COND. A A A A
DESCRIPTION MIN. Input to Output Delay Maximum Input Frequency Input Pulse Duration, High Input Pulse Duration, Low One Input Driving One Output One Output Switching 1 -- 10 10 MAX. 7.5 50 -- --
UNITS ns MHz ns ns
tpd fmax twh twl
Switching Waveforms
INP UT VALID INPUT
tw h
INP UT
twl
tpd
OU TP U T
1/
fmax
Input to Output Delay
Input Pulse Width/ Fmax
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 2ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A R1 470 R2 390 CL 50pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
7
Specifications ispGDS
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.3 2.25 2
Delta Tpd vs # of Outputs Switching
0 10
Input Clamp (Vik)
Normalized Tpd
1.2 1.1 1 0.9 0.8 4.50 4.75 5.00
PT H->L
Delta Tpd (ns)
1.25 1 0.75 0.5 0.25 0
FALL
Iik (mA)
6 7 8 9 10 11
PT L->H
1.75 1.5
RISE
20 30 40 50 60 70 80 90
5.25
5.50
1
2
3
4
5
-2.00
-1.50
-1.00
-0.50
0.00
Supply Voltage (V)
Number of Outputs Switching
Vik (V)
Normalized Tpd vs Temp
1.3 14 12
Delta Tpd vs Output Loading
7
Delta Icc vs Vin (1 input)
Normalized Tpd
Delta Tpd (ns)
10 8 6 4 2 0 -2 -4
Delta Icc (mA)
150 200 250 300
1.2 1.1 1 0.9 0.8 0.7 -55 -25
PT H->L PT L->H
RISE FALL
6 5 4 3 2 1 0
0
25
50
75
100
125
0
50
100
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Temperature (deg. C) Vol vs Iol
3 2.5 5 4
Output Loading (pF) Voh vs Ioh
4.25 4
Vin (V)
Voh vs Ioh
Voh (V)
Voh (V)
Vol (V)
2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00
3 2 1 0 0.00 10.00 20.00 30.00 40.00 50.00 60.00
3.75 3.5 3.25 3 0.00 1.00 2.00 3.00 4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.30
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
Normalized Icc
1.10
1.1
1.20
1.00
1
1.10
0.90
0.9
1.00
0.80 4.50 4.75 5.00 5.25 5.50
0.8 -55 -25 0 25 50 75 100 125
0.90 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
8

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